STAC-ML™ Pack for myrtle.ai VOLLO™ (Rev C) with Silicom Artena (AMD VP1802 FPGA) on Supermicro AS-2015CS-TNR

Type: Audited

Specs: STAC-ML™ Markets (Inference)

STAC recently performed a STAC-ML™ Markets (Inference) benchmark audit on a stack including the STAC-ML Markets (Inference) Pack for Myrtle.ai VOLLO, an Silicom Artena (AMD VP1802 FPGA) card and a Supermicro SuperServer

STAC-ML Markets (Inference) is the technology benchmark standard for solutions that can be used to run inference on realtime market data. Designed by quants and technologists from some of the world's leading financial firms, the benchmarks test the latency, throughput, energy efficiency, space efficiency, and algorithm quality of a technology stack across three model sizes and different numbers of model instances.

Compared with all other public submissions for the Tacana suite, this SUT demonstrated for all three models, in all NMI configurations, the 99p latency was lower than any previously reported for that model

Additionally, this SUT represents:

  • First sub 2μs 99p latency for LSTM_A
  • First sub 3μs 99p latency for LSTM_B
  • First sub 8μs 99p latency for LSTM_C
Further results and details can be found in the report.

The benchmark reports are available to all STAC Observer members. Additionally, Insights Subscribers have access to extensive visualizations of all test results, the micro-detailed configuration information for the solutions tested, the code used in this project, and the ability to run these same benchmarks in the privacy of their own labs. To learn about subscription options, please contact us.

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The STAC-ML Working Group develops benchmark standards for key machine learning (ML) workloads in finance. These benchmarks enable customers, vendors, and STAC to make apples-to-apples comparisons of techniques and technologies.

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