Jump to Navigation
STAC
Back to Main Stac Site
  • Research Domains
    • Tick & streaming analytics (STAC-M3)
    • Risk computation (STAC-A2)
    • Strategy backtesting (STAC-A3)
    • Artificial Intelligence (STAC-AI)
    • Machine Learning (STAC-ML)
    • Network I/O (STAC-N1, -T0)
    • Tick-to-Trade (STAC-T1)
    • Time sync (STAC-TS)
    • Cloud Communications (STAC-N2)
    • FPGA SIG
    • Data Center SIG
    • Cloud SIG
    • Time Sync SIG
  • Dashboard
  • Log in

You are here

Home » Related content

Related content

Brevan Howard

Read more

Brevan Howard

Read more

Broadridge

Read more

Broadridge

Read more

CoreWeave

Read more

Self

Read more

Bhaskar Jain

Read more

Santosh Rao

Read more

Sternberg Investments

Read more

The Edge of the Edge: PCB Latency in Trading Reaction Time

Adam Sherer, Verification Technology Executive, Cadence Design Systems, presented this at the 31 May 2023 STAC Summit in New York.

Watch the video below.

Download the slides below.

Read more

Pages

  • « first
  • ‹ previous
  • …
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • …
  • next ›
  • last »

Sign up to
Our Newsletter

(If you're a human, don't change the following field)
Your first name.
(If you're a human, don't change the following field)
Your first name.
STAC

Footer Secondary

  • Legal Terms
  • Cookies Policy
  • Privacy Policy
Back to Main Stac Site

© 2006-2026 Strategic Technology Analysis Center

STAC and all STAC names are trademarks or registered trademarks of Strategic Technology Analysis Center.